1. Field of the Invention
This invention generally relates to a liquid crystal display and, more particularly, to an integrated gate driver circuit of a liquid crystal display.
2. Description of the Related Art
A liquid crystal display controls the operation of every pixel through a plurality of gate driver circuits and source driver circuits to display images thereon. In order to improve the quality of images displayed by a liquid crystal display, the resolution thereof is increased rapidly and therefore more drive circuits are required so as to drive the liquid crystal display such that the manufacturing cost is significantly increased.
Please refer to FIG. 1, it shows a schematic diagram of a conventional liquid crystal display, wherein the gate driver circuit of a liquid crystal display 9 and a pixel matrix 91 may be simultaneously manufactured on the same substrate so as to reduce the manufacturing cost. This kind of gate driver circuit is called integrated gate driver circuit 92. The integrated gate driver circuit 92 is formed by a plurality of cascaded drive units.
Please refer to FIGS. 2a and 2b, FIG. 2a shows a circuit diagram of a drive unit 920 of the integrated gate driver circuit and FIG. 2b shows an operational timing diagram of the drive unit 920. The drive unit 920 receives an input signal “Input”, a first clock signal CK1 and a second clock signal CK2; and outputs an output signal “Output”.
Within a first time period t1, the first clock signal CK1 turns on the first switch T1 and the third switch T3 at the same time. In this period, the voltage of a node X switches from a low level to a high level to turn on the second switch T2. Since the second clock signal CK2 is at a low level within this period, the drive unit 920 outputs a low level output signal “Output”.
Within a second period t2, the second clock signal CK2 switches from a low level to a high level. Since the voltage of the node X is still at a high level in this period, the drive unit 920 outputs a high level output signal “Output”, wherein the output signal “Output” also serves as the input signal of an immediately following drive unit of the drive unit 920.
Within a third period t3, the first clock signal CK1 turns on the first switch T1 and the third switch T3 again at the same time. In this period, voltages of the node X and the output signal “Output” change to a low level. Within a fourth period t4, the second clock signal CK2 changes to a high level again, and the voltage of the node X interacts with the stray capacitance of the second switch T2 through coupling effect to generate ripples thereon, resulting in ripples on the output signal “Output”.
Accordingly, it is necessary to further provide an integrated gate driver circuit that has better output driving characteristics so as to avoid malfunction of a liquid crystal display.